Revamping Storage Class Memory with a Hardware-Automated Memory-over-Storage Solution

Hardware-Automated Memory-over-Storage serves terabyte-scale memory size and persistency by aggregating the storage capacities of non-volatile memory and high-performance SSD (Solid-state drive) into a single large memory space. It is likely to meet HPC (High-performance computer)’s expectations for high-capacity memory and stability.

Article | Fall 2021

The computing power of supercomputers is increasing exponentially by employing more computing nodes. From Edison in 2015 to Cori in 2016, computing power has increased tenfold, from 2.6 PFLOPS (peta FLOPS: peta floating point operations per second) to 27 PFLOPS. However, the scalability of the memory capacity has fallen behind this increasing computing power. For example, the overall memory capacity in Cori was increased by only 2.5 times, from 356 terabytes to 875 terabytes.

To address this issue, non-volatile dual in-line memory module technologies (NVDIMM-P and NVDIMM-N) have already been developed. NVDIMM-P technology ensures persistency by replacing DRAM with persistence memory. However, NVDIMM-P such as Optane DC PMM (Persistent memory module) exhibits 6x lower performance than DRAM and does not allow direct access to its internal DRAM, in addition to requiring OS-level support to enable persistent memory accesses. NVDIMM-N uses DRAM and flash as backup storage. When a power failure occurs, the supercapacitor is used as an energy source for DRAM backup operations. However, because capacitor size is limited, NVDIMM-N’s memory capacity is limited.

 

Prof. Myoungsoo Jung and his research team at the school of Electrical Engineering at KAIST have developed Hardware-Automated Memory-Over-Storage (HAMS), which enables terabyte-scale memory size with similar performance to NVDIMM. HAMS uses NVDIMM-N as an inclusive cache and ULL-Flash (ultra-low latency flash) as the memory backend. If the incoming memory request data resides in the NVDIMM, the NVDIMM will directly serve the memory request. Otherwise, HAMS will fetch the data from the ULL-Flash and move the data to NVDIMM. The power failure management for persistency control is central to a key design of HAMS. Specifically, HAMS integrates super-capacitors in ULL-Flash to flush data in the volatile DRAM buffer to the persistent flash media. During the power restoration, HAMS reissues all pending requests to the underlying ULL-Flash for data persistency and consistency.

However, there are two challenges from an architectural perspective. First, because NVMe uses PCIe (peripheral component interconnect express) interface, performance can be capped by PCIe bandwidth. By exposing NVMe interface and NVDIMM with the same DDR (Double data rate) interface, HAMS can solve the bandwidth issue. Second, because data need to be copied to SSD’s internal DRAM, more power is required. To reduce power consumption, HAMS removed the SSD’s internal DRAM that is used for data buffering.

 

The proposed HAMS can provide 119% higher system performance than a software-based NVDIMM design while consuming 45% less energy. HAMS is expected to replace existing memory used in data centers and supercomputers, which require large amounts of memory and are sensitive to power failures.
This research was published as a part of a conference proceeding paper at the 48th International Symposium on Computer Architecture (ISCA-48) under the title, “Revamping Storage Class Memory with Hardware Automated Memory-Over-Storage Solution.”