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Research Webzine of the KAIST College of Engineering since 2014

Fall 2025 Vol. 25
Electronics

Dual‑Mode neuransistor for on‑chip liquid‑state computing

August 26, 2025   hit 512

In this research, Professor Kyung Min Kims team developed a threeterminal neuransistor that unifies excitatory and inhibitory dynamics, enabling a hardware liquidstate machine that outperforms conventional echostate networks in terms of chaotic timeseries predictions.


 The neuransistor exhibiting hybrid excitatory and inhibitory neural dynamics and its application in the brain-like LSM.  *Liquid-state machine (LSM): a spiking neural network model that emulates the dynamic properties of biological neural networks, processing time-varying input data.

 

The neuransistor chip, developed at KAIST, stores and computes data in the same physical spot, allowing it to generate both excitatory and inhibitory signals like a brain cell and to decode complex timeseries streams in real time. A neuransistor, a newly coined term combining "neuron" and "transistor," reproduces key neuronal behaviors. By eliminating the rigid separation between memory and logic that has constrained conventional computers, the device ushers in a far more efficient breed of AI hardware.

 

Standard digital machines excel at handling static images or numerical data, yet they struggle with continuous inputs such as speech, heart rate traces, or drone sensor data. These signals must be divided into frames and fed to powerhungry neural networks. The neuransistor, in contrast, processes the raw flow directly. It is fabricated by stacking nanometerthin titanium oxide (TiO) and aluminum oxide (AlO) films. A highly mobile twodimensional electron gas (2DEG) forms at the interface between these two materials and serves as the transistor channel. A positive gate pulse releases lightly trapped electrons and increases the conductivity, producing an excitatory state. A negative pulse traps carriers and suppresses the current, creating an inhibitory state. Both responses fade within milliseconds, allowing the device to reset itself without external intervention.

 

A small bias on the source terminal finely tunes the amplitude and duration of each spike. Stepping the bias through a series of values generates dozens of internal states in a single device, exactly what a liquidstate machine (LSM) needs to transform raw data into rich patterns. External randommask circuits are therefore unnecessary, simplifying the hardware design. 
Figure 1: The neuransistor-based LSM simulation. Configuration of the reservoir using a 1×N neuransistor array with ML time-multiplexed input signals. Predicted 3D state trajectories and the results for the LSM using a Lorenz attractor.
To evaluate the performance capabilities, the researchers wired twelve neuransistors into a minimal LSM reservoir and assessed two benchmarks. On the Henon chaotic time-series, the hardware achieved a normalized rootmeansquare error (NRMSE) of 0.0097, roughly ten times lower than a software echostate network of equal size (0.1020). For the Lorenz attractor, the neuransistorbased LSM reached an NRMSE of 0.03, again outperforming its software counterpart. After more than one million operating cycles, the device characteristics remained stable and the variation among devices was small, confirming robust endurance and manufacturing uniformity.

 

The neuransistor’s oxide bilayer is fabricated via low-temperature atomic layer deposition (<300°C), ensuring compatibility with standard semiconductor processes and flexible substrates. These devices can be integrated with sensors to process signals locally without sending data to external servers. Their CMOS compatibility and operational stability make them ideal candidates for on-chip liquid-state machine reservoirs.

 

“A Neuransistor with Excitatory and Inhibitory Neuronal Behaviors for Liquid State Machine was published in Advanced Materials on April 8, 2025.